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| publication number s71ns-ja0_00 revision a amendment 6 issue date september 22, 2005 s71ns128ja0/s71ns064ja0 stacked multi-chip product (mcp) 128 megabit (8 m x 16-bit) a nd 64 megabit (4 m x 16-bit), 110 nm cmos 1.8 volt-only simultaneous read/write, burst mode flash memories with 16 megabit (1m x 16-bit) psram data sheet advance information ii s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information notice on data sheet designations ! " !# ! ! ! ! $ % " " " !$ " ! ! " & ' " ( " ! # ! ! $# $ $) " " & ' *+ $ # $ ! $ # # ! $$$# " ( $ * " ! !, + ! ! ! $ - $* $ + . $ ) ! / $ $ $! ! ! !0 1 " & ' *+ $ $ $" # ) 2 ! ! $ ( 3 $ 4 ,5 publication number s71ns-ja0_00 revision a amendment 6 issue date september 22, 2005 distinctive characteristics !"# $% !"& !"'( )%* +, 6 789:) 3789 3: 6 $0 ; -; +- % 6 $ $ ) < $ 6 = $ (.)/0 1 234% 6 > 7?8 6 @: 6 a@8 5 6 6 $ 6 a<7b $ 6 a<7b $ 7 % % $# 76 $ 1 234% 6>4d &c8 6 1 &e: 6 <- &78 6 $&fg 6 6 ,ah 6 " * cf/7cai+ " *cf/:bei+?ch 6,$ 6 6 0 j0 / 6 8 6 $ $ d k %% 6) 7 % 76 9: :.;". 6 > $ cf, cf0 ) !!4% 6 )!44$444 % : ! % % ;4 % : 6 6 -$- $ 6 -$ < 6 : % + 6 ! ! $ ! / 7 % : :=< 6 2 ), % % % 8 > .#? @ =6 5a &! !;#94 > ..? @ =6 5a &! 4b.94 s71ns128ja0/s71ns064ja0 stacked multi-chip product (mcp) 128 megabit (8 m x 16-bit) and 64 megabit (4 m x 16-bit), 110 nm cmos 1.8 volt-only simultaneous read/write, burst mode flash memories with 16 megabit (1m x 16-bit) psram data sheet advance information 2 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information contents notice on data sheet designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii product selector guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 physical dimensionsCs71ns128ja0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 nla04848 -ball very thin fine-pitch ball grid array (fbga) 10 x 11 mm package ...........................................10 nlb04444 -ball very thin fine-pitch ball grid array (fbga) 9.2 x 8 mm package .......................................... 11 device history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 appendix b: daisy chain information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 psram characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 psram device bus operations ................................................................................................... ............................................ 16 psram dc characteristics ...................................................................................................... ................................................ 16 psram ac characteristics ...................................................................................................... ................................................. 16 psram device operation ........................................................................................................ ................................................. 17 psram read access ............................................................................................................. ...................................................... 17 psram write access ............................................................................................................ ..................................................... 17 configuration register access ................................................................................................. ................................................ 17 revision summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 ta b l e s table 1 configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figures figure 1 nla048 daisy chain layout (top view, balls facing down) ................................................................. ................................... 14 figure 2 nlb044 daisy chain layout (top view, balls facing down)................................................................ ..................................... 15 figure 3 configuration register read access.................................................................................... .............................................................. 18 figure 4 configuration register write access ................................................................................... .............................................................. 18 figure 5 psram read cycle 1 (we# = vih)........................................................................................ ............................................................. 19 figure 6 psram read cycle 2 (we# = vih)........................................................................................ ............................................................ 19 figure 7 psram write cycle 1 (oe# = vih)....................................................................................... ............................................................ 20 figure 8 psram write cycle 2 (oe# = vih)....................................................................................... .......................................................... 20 4 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information product selector guide &! !;#94$ &! 4b.94 )) 4!$43$!!$;!$;3 5 c (.)/0 6) , 4 <4/$ cf/7cai<::!cf/:bei<:: , 1 : 4 ) ! * +a@8 4 )> ! * > +7?8 4 ) ! * + @: 4 )-; ! * - + 4 )1-; ! * 1- +7?8 % ) 4 ) ! * c +f: 4 )-; ! * ? +f: 4 )1-; ! * 1- +8: september 22, 2005 s71ns-ja0_00_a6 s71ns128ja0/s71ns064ja0 5 advance information mcp block diagram !" !" # $ % & , 4 *cf/7cai cf/:bei+ d--; 0 -; 1-; .-; 0 ; 7b4$ d4 d k h 7f"7b c: c7 c7<>; >; * /7 +cc 6 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information connection diagram a1 rdy a2 a21/lb# a3 gnd a4 clk a5 v cc a6 we# a7 v pp a8 a19 a9 a17 a10 a22/ub# b1 v cc b2 a16 b3 a20 b4 avd# b5 nc b6 reset# b7 cs# b8 a18 b9 ce# b10 gnd c1 gnd c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 gnd d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v cc d9 a/dq1 d10 a/dq0 nc nc nc nc nc nc nc nc &! !;#94 ea"> 0 ,>m*/:ea+ 0 !> , september 22, 2005 s71ns-ja0_00_a6 s71ns128ja0/s71ns064ja0 7 advance information connection diagram a1 rdy a2 a21/lb# a3 gnd a4 clk a5 v cc a6 we# a7 v pp a8 a19 a9 a17 a10 ub# b1 v cc b2 a16 b3 a20 b4 avd# b5 nc b6 reset# b7 cs# b8 a18 b9 ce# b10 gnd c1 gnd c2 a/dq7 c3 a/dq6 c4 a/dq13 c5 a/dq12 c6 a/dq3 c7 a/dq2 c8 a/dq9 c9 a/dq8 c10 oe# d1 a/dq15 d2 a/dq14 d3 gnd d4 a/dq5 d5 a/dq4 d6 a/dq11 d7 a/dq10 d8 v cc d9 a/dq1 d10 a/dq0 nc nc nc nc &! 4b.94 ee"> 0 ,>m*/>:ee+ 0 !> , 8 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information input/output descriptions cc !d4l > *cc $ 7ca4$, + c7<>; j !d4 > c:97b j < 3789< 3: j 4) < < ; j d4 -; j , - $ h > 1-; j 1- $ h > .-; j .- $ 0 j *7@097f80+ m/ j m / j / n d k j d n > 0 1 j h j , h 5 0 ; $ !$# h h 0 ; j 0 * $789 : )! $cc97b + 0 j ! n $! $ h 0 2 j d--; j 2 0 j 0 j 7c0! n $ 0 ! $ $ 0 2 logic symbol 7b < 3789 < 3: c:97b -; 1-; .-; d--; h d k 0 ; ; 0 occ $ 7ca4$, c7<>; occ september 22, 2005 s71ns-ja0_00_a6 s71ns128ja0/s71ns064ja0 9 advance information ordering information $*0 $ + $ & @ $ $ $ $ '( %)& ) & &* %) & & & s71ns 128 j a0 ba w 01 0 da=e: : j c j @" d ? j 7?" d =,1, : a,=, :7 j 8e42%, !f: !-4 d4*-?+ :? j 8e42%, !f: !-4 d4*-e+ 77 j 8e42%, !f: !d4*7+ c7 j 8e42%, !f: !4 d4*4c+ c? j 8e42%, !f: !4 d4*4?+ =:): =f : a: . j .*9c8 pa8 + , *9e: pa8 +! da:=e: > j very thin fine-pitch bga * $+", >, j very thin fine-pitch bga * $+", >i j very thin fine-pitch bga * $+",,?8 % ) : =e : j 7b4 $*74)7b">+ 1 / ,: =:/,1,ae i j 77: , m 1 / : =e 7ca j 7ca4 $*a4)7b">+ :be j be4 $*e4)7b">+ :@:)1e @7/j 4" ! d <.!>4, 4 4) <1 7a"01 !> ! d4 @ @7/ 7ca i : >!>,!>i . :7!:?!77!c7!c? :!c!? :be 10 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information physical dimensionsCs71ns128ja0 nla04848-ball very thin fine-pitch ball grid array (fbga) 10 x 11 mm package % '*+ ,*- ' %* % + & package nla 048 jedec n/a 9.95 mm x 10.95 mm nom note package symbol min nom max a 1.05 --- 1.20 overall thickness a1 0.20 --- --- ball height a2 0.85 0.91 0.97 body thickness d 9.85 9.95 10.05 body size e 10.85 10.95 11.05 body size d1 4.50 bsc. ball footprint e1 1.50 bsc. ball footprint md 10 row matrix size d direction me 4 row matrix size e direction n 48 total ball count b 0.25 0.30 0.35 ball diameter e 0.50 bsc. ball pitch sd / se 0.25 bsc. solder ball placement --- depopulated solder balls 3297 \ 16-038.22a1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (excep t as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. top view bottom view side view index mark a1 corner nf4 nf1 nf8 1 2 43 5 6 8 97 nf2 nf3 a b nf7 nf5 c d 10 nf6 d a 10 e a1 corner se 7 e1 d1 e 1.00 1.00 7 sd b 6 b c m c m 0.15 0.05 a 1.00 1.00 c 0.10 c 0.08 a b c a2 seating plane a1 september 22, 2005 s71ns-ja0_00_a6 s71ns128ja0/s71ns064ja0 11 advance information physical dimensionsCs71ns064ja0 nlb04444-ball very thin fine-pitch ball grid array (fbga) 9.2 x 8 mm package % '*+ ,*- ' %* % + & package nlb 044 jedec n/a 8.00 mm x 9.20 mm nom note package symbol min nom max a 1.05 --- 1.20 overall thickness a1 0.20 --- --- ball height a2 0.85 0.91 0.97 body thickness d 7.90 8.00 8.10 body size e 9.10 9.20 9.30 body size d1 4.50 bsc. ball footprint e1 1.50 bsc. ball footprint md 10 row matrix size d direction me 4 row matrix size e direction n 44 total ball count b 0.25 0.30 0.35 ball diameter e 0.50 bsc. ball pitch sd / se 0.25 bsc. solder ball placement --- depopulated solder balls 3298 \ 16-038.22a1 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (excep t as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. 10 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. a1 corner index mark d a 10 e a1 seating plane c 0.10 a2 c b a c 0.08 nf1 nf3 2 1 3 4 5 6 987 10 a nf2 c d nf4 b e 1.00 se e1 d1 sd b 1.00 a m m c c 0.05 0.15 b a1 corne r 7 7 6 12 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information device history . % +) @ 8 ) 8 : :* /* ) g 6 !;#h!b:)1 @7/7cai:>.:: 7- @7c- -!-4 c*a8 +!bb42% 0 2 @7/7cai:>.:7 7- @77- -!-4 c*a8 +!8e42% 0 2 @7/7cai:>,.:7 c-?- @77 -!-4 ?*a8 +!8e42% ,)$ @7/7cai:>,.:7 c-? @777 $ -4 ?*a8 +!8e42% ,)$ @7/7cai:>.:c ?-e- @7c -!-4 e*@: +!8e42% / @: -1a8 @7/7cai:>,.:c @7/7cai:>,.:? ?-e @777 !-4 e*@: +! 8e42%/ @: -1a8 !;#h!b) @7/7cai:>.c7 @77 -!4 c*a8 +!8e42% @7/7cai:>,.c7 @7/7cai:>.c7 ?4c @777 !4 c*a8 +!8e42% @7/7cai:>,.c7 @7/7cai:>,.c? ?4?- @77> -!4 ?*@: +!8e42% / @: -1a8 @7/7cai:>,.c? ?4? @777 !4 ?*@: +!8e42% / @: -1a8 b.h!b:)1 @7/:bei:>.:7 7-?- @77- -!-4 ?*a8 +!8e42% ,)$ @7/:bei:>,.:7 7-? @777 !-4 ?*a8 +!8e42% ,)$ @7/:bei:>.:c c-e- @7c -!-4 e*@: +!8e42% / @: -1a8 @7/:bei:>,.:c @7/:bei:>,.:? c-e @777 !-4 e*@: +!8e42% / @: -1a8 b.h!b) @7/:bei:>.c7 7- @77- -!4 c*a8 +!8e42% @7/:bei:>,.c7 @7/:bei:>.c7 c4c @777 !4 c*a8 +!8e42% @7/:bei:>,.c7 @7/:bei:>,.c? c4?- @77 -!4 ?*@: +!8e42% / @: -1a8 @7/:bei:>,.c? c4? @777 $ 4 ?*@: +!8e42% / @: -1a8 september 22, 2005 s71ns-ja0_00_a6 s71ns128ja0/s71ns064ja0 13 advance information appendix a: daisy chain information 6 8 ) 8 6 % !;#+!b)) 6 % * $+" , & ff /:ea4::c ff /:ea4:: $ @7/7cai: 7ca"4$77: , 7b"4$d4 * $+",& ff /:ea4,::c ff /:ea4,:: %=%+ 14.# :c8p ::8 1 $ ", k 3 d 88:*?:: $ # + 79 7 b9 b 7:9>7: 89>8 c9 c @9 @ f9>f e9>e ?9 ? a9 a a9>a ?9>? e9 e f9 f @9>@ c9>c 89 8 7:9 7: b9>b 79>7 1 $ /,7 9 /,e /,c 9 /,8 /,7b 9 /,7f /,7@ 9 /,c: 14 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information figure 1 nla048 daisy chain layout (top view, balls facing down) 1 2 3 4 5 6 7 8 9 10 a b c d nf16 nf17 nf4 nf5 nf2 nf20 nf1 nf19 september 22, 2005 s71ns-ja0_00_a6 s71ns128ja0/s71ns064ja0 15 advance information appendix b: daisy chain information figure 2 nlb044 daisy chain layout (top view, balls facing down) 6 8 ) 8 6 % !;#+!b)) 6 % * $+", & ff />:ee4::c ff />:ee4:: $ @7/:bei: be"4$77: , 7b"4$d4 * $+",& ff />:ee4,::c ff />:ee4,:: %=%+ 154.. :c8p ::8 1 $ ", k 3 d b::*?:: $ # + 79 7 b9 b 7:9>7: 89>8 c9 c @9 @ f9>f e9>e ?9 ? a9 a a9>a ?9>? e9 e f9 f @9>@ c9>c 89 8 7:9 7: b9>b 79>7 , /,79/,? /,c9/,e 1 2 3 4 5 6 7 8 9 10 a b c d nf3 nf4 nf1 nf2 16 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information psram characteristics psram device bus operations /0/& %120/& %1$0!3 % psram dc characteristics psram ac characteristics < ,:< -:< 15< f5< @ < i!'?!bj + k i!( l 4j ) 7 2 q q q q q q 2 m2"= $ 22qq 2 q 2 m2"=1 $ q q22 q q 2 m2"=1 $ 2 2 2 2 q d . 2 2 2 2 q 1 d d 2 2 2 2 2 2 2 q 1 >d 2 2 2 q 1 l>d 2 2 q 1 .d 2 2 2 q >. 2 2 2 q l>. 2 2 q .. = ) =% ) * f 0 / j0 0 "7 7 g 1 1 ;j0 2 1-;j0 2 .-;j0 ! 0 1 j0 0 "7 7 g 7 1 j7g!7::r! 1 j:! ; :c0!0 / :c00 / 0 9:c0 ? c j4 ! 1 j:!7::r! ;j0 !0 / j0 2 0 c8 0 1 1 0 1 j:7 :7 0 0 12 12 0 12 j":7 0 39:70 0 >7 $ *41+ ; 0 9:c0!1 j:s0 b: g 1 &4 '4 f ) ) * ) ) * 0 ; 0 78 7::: c: 0 ; 0 78 c: 0 ; 0 2 88 $0 ; @7: 0 ; 0 7 @: f: c @: f: - $ ? @: f: $ $ 1- :: 1 $ 1- c8 8: l>;!>; $ l>> c8 e: l>;!>; $ "= >= 878 1 $ "= 1= 878 $2 "= 2= 78 c: l>;!>; $2 "= >2= 78 78 1 $2 "= 12= 78 78 - 0 ; .7 @: f: .c @: f: $ .? @: f: . .d e8 @: l>;!>; >. 8: @: . c8 ?8 2 :: september 22, 2005 s71ns-ja0_00_a6 s71ns128ja0/s71ns064ja0 17 advance information psram characteristics psram device operation $ > ! *;+" $ $ $! 0 ; ; $ > !) < $< 3t78":u " 1- $ $ $ psram read access * , 8 , b + $ " ) < $< 3t78":u $t7f"7bu. $! *;+ !0 ; $ $ " $ 0 ; 0 ; > 1-; $ l>; >; psram write access * , @ , a + $ ) < $< 3t78":u $t7f"7bu. $! *;+ !0 ; $ $ $ 0 ; 0 ; > ! " ) < $. -; l>; >; configuration re gister access d4 7b$ $ >; l>; " 0 ; , ? , e $ $ 7 . $78"a! 18 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information psram characteristics configuration re gister access (continued) figure 3 configuration register read access figure 4 configuration register write access table 1 configuration register 5 8 78 9 a v @ 9 e d ? 9 c d % ::j, :7j7 a/dq15-0 cs# oe# lb#, ub#, we# high don't care data valid t acc3 t oe a/dq15-0 cs# we# lb#, ub#, oe# data valid acc3 wrl t t september 22, 2005 s71ns-ja0_00_a6 s71ns128ja0/s71ns064ja0 19 advance information psram characteristics psram read access timing diagrams figure 5 psram read cycle 1 (we# = v ih ) 4 56 0 .'/' 01 7!8 & & 568 7!8 & & .'89/'8 # - & ++ % : 1 % &; ++ < ++ % : figure 6 psram read cycle 2 (we# = v ih ) a/dq15-0 cs# oe# lb#, ub#, we# high don't care data valid t acc3 t oe t adoe t avds cs# a ddress/data ub#, lb# oe# t avd address valid data valid t css t ublba a vd# ab t bhz t hz t ohz t olz t blz t avdh c t acc2 t oe 20 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information psram characteristics psram write access timing diagrams figure 7 psram write cycle 1 (oe# = v ih ) %% & = ; >?/ < +*81 >68 .'8/'8 & & +*8 >68 &.'8 /'8 & &.'8 /'8 & &+*8 &>68 4 >?/ & & figure 8 psram write cycle 2 (oe# = v ih ) t avdh t avds cs# address/data ub#, lb# we# t acw3 t acw1 t avd t css t bw avd# a b c t dw t dh data valid address valid t wrl t avdh t avds cs# address/data ub#, lb# we# t avd t css t bw avd# a b c t dw t dh data valid address valid t wrl t acw2 september 22, 2005 s71ns-ja0_00_a6 s71ns128ja0/s71ns064ja0 21 advance information revision summary revision a0 (december 8, 2003) d revision a1 (february 5, 2004) a a 4 4/$ , l 1 4 /$ 0 $ 4 $ / l 4/$ % ) 5 ,% d d <. 4 revision a2 (m ay 7, 2004) 6 revision a3 (november 17, 2004) 8 =% revision a4 (march 21, 2005) a 4 4/$ % )6 , / l revision a5 (august 3, 2005) a dbb42% , -4 4 d4d" bb42% / l revision a6 (september 22, 2005) , ,?8 @ l 22 s71ns128ja0/s71ns064ja0 s71ns-ja0_00_a6 september 22, 2005 advance information colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contem plated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and c ould lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear re action control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerabl e (i.e., submersible repeater and artificial satellite). please note that spansion will not be liab le to you and/or any third party for any claims or damages ari sing in connection with above- mentioned uses of the products. any semiconductor device has an inherent chance of failure. you must protect against injury, da mage or loss from such failures by incorporating safety design meas ures into your facility and equipment such as redundancy, fire protection, and prev ention of over-current levels and other abnormal operatin g conditions. if any products described in this docu ment represent goods or technologies subject to certain restrictions on ex- port under the foreign exchange and foreign trade law of japan, th e us export administration regu lations or the applicable laws of any other country, the prior authorization by the respective government en tity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion llc pro duct under development by spansion llc. spansion llc reserves the right to change or discontinue work on an y product without notice. the information i n this document is provided as is without warranty or guarantee of any kind as to its accu racy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. spansion llc assu mes no liability for any damages of any kind arising out of the use of the information in this document. copyright ?2003-2005 spansion llc. all rights reserved. spansion, the spansion logo, and mirrorbit are trademarks of spansion l lc. other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies . |
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